In recent years, DC-DC converters have been used frequently in power supplies for the CPUs of personal computers and other power supplies. For example, a step-down DC-DC converter, supplying a DC voltage controlled so as to be lower than its power supply voltage to a load, comprises an inductor, and a high-side FET and a low-side FET connected in series between the power supply voltage and the ground voltage. These high-side and low-side FETs repeat ON/OFF operations alternately. As a result, the inductor repeats the storage and release of magnetic energy. The AC voltage generated when the storage and release are repeated in the inductor as described above is rectified, and a predetermined voltage is supplied to the load. The voltage supplied to the load is adjusted according to the ratio of the ON time in one period of the switching operation of the high-side FET. The inductor current has a triangular wave shape in which the current value increases/decreases repeatedly depending on the ON/OFF switching operation. In the current mode control system, the ON time or the OFF time of the high-side FET is usually controlled by controlling the peak value or the valley value of the current.
In the peak value control system in which the ON time is controlled, it is necessary to detect the current flowing through the high-side FET on the power supply voltage side. Hence, a detector and its peripheral circuit are provided on the power supply voltage side. As a result, the circuit configuration for carrying out accurate current detection in the case that the power supply voltage is assumed to fluctuate inevitably tends to become complicated.
On the other hand, in the valley value control system in which the OFF time is controlled, the current flowing through the low-side FET on the ground side is detected. Hence, a detector and its peripheral circuit are provided on the ground side, and the circuit configuration can be simplified.
Furthermore, because the output voltage tends to become lower recently, the ON time of the high-side FET tends to become shorter. In the peak value control system in which the ON time is controlled, detection and control must be carried out in a short time during which the high-side FET is ON. On the other hand, in the valley value control system in which the OFF time is controlled, detection and control should only be carried out in a time during which the high-side FET is OFF. The control time can thus be made longer. For the above-mentioned reasons, such a valley value control system as disclosed in Japanese Patent Application Laid-Open No. 2001-136737 has been proposed.
As an example of the valley value control system in which the OFF time of the high-side FET is controlled, the control system disclosed in Japanese Patent Application Laid-Open No. 2001-136737 will be described below referring to FIG. 6.
FIG. 6 is a circuit diagram of a conventional step-down DC-DC converter. The DC-DC converter shown in FIG. 6 comprises a high-side FET 11, a low-side FET 12, an inductor 13, an output capacitor 14, an error amplifier 15, a current detector 16, a comparator 17, a timer circuit 18, and an RS latch 19. This conventional DC-DC converter is configured so that a voltage Vi is applied to the input terminal and so that a voltage Vo is supplied from the output terminal to a load. In FIG. 6, Vr designates a reference voltage.
The high-side FET 11 and the low-side FET 12, serving as switching devices, are connected in series between the input voltage Vi and the ground potential. The inductor 13 and the output capacitor 14 are connected between the connection point of the switching devices and the output terminal Vo so as to form a filter. The high-side FET 11 and the low-side FET 12 are connected to the RS latch 19 so as to respectively turn ON/OFF complementarily. The reference voltage Vr is input to the noninverting input terminal (+) of the error amplifier 15, the output voltage Vo is input to the inverting input terminal (−) thereof, and the error amplifier 15 outputs an error signal Ve to the noninverting input terminal (+) of the comparator 17. The error signal Ve is input to the noninverting input terminal of the comparator 17, and the comparator 17 outputs a set signal S for setting the RS latch 19. The current detector 16 detects the current flowing to the inductor 13 via the low-side FET 12 when the low-side FET 12 is ON. The current detector 16 detects and amplifies the voltage drop due to the ON resistance of the low-side FET 12, and generates and outputs a voltage-converted current detection signal Vc. This current detection signal Vc is applied to the inverting input terminal (−) of the comparator 17. An external clock signal CK is input to the reset input terminal of the RS latch 19.
Next, the basic operations of the conventional DC-DC converter shown in FIG. 6 will be described below.
When the high-side FET 11 is ON, the voltage difference (Vi−Vo) between the input voltage Vi and the output voltage Vo is applied to the inductor 13. At this time, the current IL flowing through the inductor 13 increases linearly, and magnetic energy is stored in the inductor 13. When the high-side FET 11 is OFF, the output voltage Vo is applied to the inductor 13 in the opposite direction. At this time, the inductor current IL decreases linearly, and the inductor 13 releases the magnetic energy. The inductor current IL is smoothened using the output capacitor 14, and a smoothened DC current is supplied to the output terminal. The output voltage Vo is fed back to the inverting input terminal (−) of the error amplifier 15, and the reference voltage Vr is input to the noninverting input terminal (+) of the error amplifier 15. The error signal Ve being output from the error amplifier 15 is input to the noninverting input terminal (+) of the comparator 17. The current detection signal Vc obtained by subjecting the current flowing through the low-side FET 12 to current-voltage conversion is input to the inverting input terminal (−) of the comparator 17. When the inductor current IL decreases, and when the current detection signal Vc lowers to the error signal Ve being output from the error amplifier 15, the output of the comparator 17 is inverted. In other words, the set signal S of the RS latch 19 becomes high, and the high-side FET-11 is turned ON. Then, the inductor 13 is begun to be charged. The clock signal CK is input to the reset input terminal of the RS latch 19, and the high-side FET 11 is turned OFF after a predetermined time has passed.
In the conventional DC-DC converter configured as described above, the high-side FET 11 and the low-side FET 12 are turned ON/OFF complementarily using the signals of the error amplifier 15, the comparator 17 and the RS latch 19, and the predetermined DC output voltage Vo is output.
The above-mentioned operations are the basic operations of the respective components of the conventional DC-DC converter. Operations when the load changes abruptly will be described below.
For example, when the output voltage Vo becomes lower than a target value because of the increase in the output current Io from the output terminal, the error amplifier 15 detects the lowering of the output voltage Vo and raises the error signal Ve. At this time, the time during which the current detection signal Vc of the low-side FET 12 lowers and reaches the error signal Ve, that is, the OFF time of the high-side FET 11, becomes shorter. As a result, the power supplied to the output capacitor 14 increases, and the output voltage Vo having been lowered rises.
In the opposite case, that is, when the output voltage Vo rises because of the decrease in the output current Io, the error amplifier 15 lowers the error signal Ve. At this time, the time during which the current detection signal Vc of the low-side FET 12 reaches the error signal Ve, that is, the OFF time of the high-side FET 11, becomes longer. As a result, the power supplied to the output capacitor 14 decreases, and the output voltage Vo having increased lowers.
As described above, when the load changes abruptly, the conventional DC-DC converter shown in FIG. 6 operates so that the output voltage Vo is maintained at a predetermined value.
FIG. 7 is a circuit diagram showing a circuit example of the current detector 16 that detects the current of the low-side FET 12 in the DC-DC converter shown in FIG. 6, specifically configured using a conventional technology. Because the voltage at the drain of the low-side FET 12, that is, the voltage at the current detection point, is negative, it is difficult to directly detect and amplify the voltage. Hence, as shown in FIG. 7, the current detector 16 comprises an FET 160, which is an N-channel FET being the same as the low-side FET 12, and the drain and the gate of which are common to those of the low-side FET 12, respectively; an NPN transistor 161, the emitter of which is connected to the source of this FET 160; an NPN transistor 162, the collector and the base of which are connected to the base of this NPN transistor 161 so as to form a mirror structure, and the emitter of which is connected to the source of the low-side FET 12; a current source 163 that supplies a current to this NPN transistor 162; a PNP transistor 164 and a PNP transistor 165 connected so as to form a mirror circuit, which is connected to the collector of the NPN transistor 161 and in which a current being equal to the current flowing through the NPN transistor 161 flows; and a resistor 166 that converts the current flowing through the PNP transistor 165 into a voltage. The size of the FET 160 is 1/n of that of the low-side FET 12, that is, the ON resistance of the FET 160 is n times that of the low-side FET 12. The mirror ratio is set so that the current flowing through the PNP transistor 165 is equal to the current flowing through the NPN transistor 161. The resistance value of the resistor 166 is Rs.
The potential at the source of the FET 160 and the emitter of the NPN transistor 161 becomes equal to the potential at the source of the low-side FET 12 because the NPN transistor 161 and the NPN transistor 162 form a mirror circuit. Hence, the voltage across the source and the drain of the FET 160 becomes equal to the voltage across the source and the drain of the low-side FET 12. In addition, because the ON resistance of the FET 160 is n times the ON resistance of the low-side FET 12, when it is assumed that the current flowing through the low-side FET 12 is IL when the low-side FET 12 is ON, the current flowing through the FET 160 is IL/n. This current IL/n flows through the resistor 166 via the NPN transistor 161, the PNP transistor 164 and the PNP transistor 165. As a result, a voltage Vc=Rs×IL/n is generated across the terminals of the resistor 166. In other words, the current IL that flows through the low-side FET 12 when the low-side FET 12 is ON can be detected according to the voltage across the terminals of the resistor 166.
However, in the DC-DC converter conforming to the conventional valley value control system, only the current flowing from the source to the drain of the low-side FET 12 when the low-side FET 12 is ON can be detected in the configuration of the current detector 16 shown in FIG. 7 and described above. Hence, in the DC-DC converter conforming to the conventional valley value control system, the low-side FET 12 is turned OFF when the valley value of the inductor current reaches zero. Because the ON time Ton of the high-side FET 11 in the DC-DC converter is constant, there is a problem that the output voltage Vo rises, exceeding the target value. Hence, it is necessary to carry out intermittent operation in which the high-side FET 11 is not turned ON for a predetermined time after the low-side FET 12 was turned OFF. In other words, in the case that, because the load becomes light, the valley value of the inductor current reaches zero, and the output voltage Vo exceeds the target value, the OFF state of the high-side FET 11 is maintained. When it is detected that the output voltage Vo has lowered to the target value, the high-side FET 11 is turned ON. This kind of intermittent operation has a problem that, as the load becomes lighter, the output voltage Vo rises higher owing to the charging of the output capacitor 14. Hence, as the load is lighter, the output ripple voltage that is superimposed on the output voltage Vo becomes larger, and the output ripple voltage is added to the target value. As a result, an error occurs between the output voltage Vo and the target value.